Youhanna Dimian
Seeking Summer ’27 internship opportunities

Silicon & Logic. Photography & Light.

I’m Youhanna Dimian, an Electrical Engineering student at the University of Waterloo. Welcome to my dual portfolio, showcasing my hardware and ASIC design projects alongside my photography.

See my work View photographs
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§ 01

About

Youhanna Dimian standing on a misty riverbank at Mount Rainier
Fig. 02 — Mount Rainier, Washington

Designing logic.
Capturing light.

I’m an Electrical Engineering student at the University of Waterloo building a career in ASIC design. My work centers on RTL, hardware verification, and system architecture, and I currently design digital logic for the UW-ASIC team.

My background spans the hardware stack, from writing SystemVerilog for custom silicon to designing and bringing up board-level systems. No matter the scale, my approach is the same: model it rigorously, verify it, then trust it. Off the clock, I shoot photography, applying that same technical precision to capturing light.

Studying
BASc Electrical Engineering, ’29
Focus
RTL design · Verification · ASIC
Next
Digital IC Design Intern, NXP

Technical skills

skills_top · floorplan view

RTL & logic design

SystemVerilog · Verilog · VHDL · FSM & datapath design · synthesis · static timing analysis · clock domain crossing · computer architecture

Verification

cocotb · Verilator · Icarus Verilog · self-checking testbenches · waveform analysis · GitHub Actions CI

Board & circuits

Altium Designer · PCB layout · bring-up & debug · LTspice · DC-DC converters · scope & logic analyzer

Software

C/C++ · Python · RISC-V assembly · MATLAB / Simulink · Bash

FPGA

Quartus Prime · Intel MAX10

Protocols

SPI · I²C · UART · CAN · MMIO

Photonics

PIC design · waveguides

Laid out like a chip floorplan · block area ≈ where the hours go
§ 02

Selected projects

Every design is a set of constraints
Chip layout of the SPI-PWM peripheral: rows of standard cells with metal routing, rendered from the GDS file P—01 · Featured ASIC Explore the layout in 3D GDS · Sky130
RTL design · Verilog · cocotb

SPI-controlled PWM peripheral

Sixteen independently controllable PWM outputs driven over three pins. Verilog RTL on a Tiny Tapeout tile.

Constraint
SPI arrives with no relationship to the chip’s 10 MHz clock. Sampling it directly risks metastability and a corrupted register on silicon that can’t be patched.
Solution
Two-flop synchronizers, with SCLK oversampled rather than used as a clock, so the whole design stays in one clock domain.
16PWM outputs
3SPI pins
8-bitDuty cycle
P—02 FPGA
VHDL · Quartus · Intel MAX10

4-bit ALU on FPGA

A modular ALU built from multiplexers, logic units and a ripple-carry adder, taken from RTL to real hardware.

Constraint
Prove it works on silicon, not only in simulation.
Solution
Testbenches first, then Quartus Fmax and critical-path analysis, then a MAX10 driving LEDs and 7-segment displays.
P—03 FPGA
VHDL · Moore FSM · FPGA

Traffic light controller

Dual-direction traffic control with pedestrian override, as a multi-state Moore FSM.

Constraint
A pedestrian button is an asynchronous input that can land mid-cycle, metastable.
Solution
2-DFF synchronizers and holding registers in front of the FSM.
P—04 PCB
Altium Designer · Power conversion

Buck converter PCB

A 12 V → 3.3 V, 2 A synchronous buck converter for a 10–15 V battery input, from datasheet calculations to a DRC-clean two-layer board.

Constraint
Switching regulators are noisy: fast current edges in the input loop and switch node radiate if the layout is careless.
Solution
Minimized switch-node area and input-loop inductance, with dual-sided ground pours and stitching vias.
§ 03

Experience

Co-op terms, newest first

  1. IncomingJan — Apr 2027Winter co-op

    Digital IC Design Intern

    NXP Semiconductors

    Joining NXP for my winter 2027 term in digital IC design. It's the next step from student tapeouts toward production silicon.

  2. Design teamAug 2026 — Present

    ASIC Digital Designer

    UW-ASIC Design Team · TinyTracer

    • Implementing the Ray Generator in SystemVerilog: camera rays with per-pixel jitter for anti-aliasing, plus matte, mirror and glass bounces (reflection and refraction), all in 16-bit fixed point.
    • Designed a finite state machine that runs each ray as a short sequence of operations on the chip’s shared math unit over a valid/ready handshake, so the block needs no multipliers or dividers of its own.
    • Verified it with a self-checking SystemVerilog testbench in Verilator, checking results and cycle counts against a floating-point reference across 1,000+ random and edge-case rays, and through the team’s Tiny Tapeout CI on IHP 130 nm.
    • SystemVerilog
    • Verilator
    • Fixed-point
    • Tiny Tapeout
    • IHP 130 nm

  3. May — Aug 2026

    Electrical Design Intern

    EXP Global Inc.

    • Designed building electrical systems in Revit across 6 projects: power and lighting layouts, panel schedules and single-line diagrams.
    • Sized feeders and equipment with load and voltage-drop calculations under fixed code constraints.
    • Worked through 4–6 review cycles per project with architectural and mechanical teams, resolving coordination conflicts before release.
    • Revit
    • Load calculations
    • Single-line diagrams
    • Code compliance

  4. Sep — Dec 2025

    Electrical Engineering Intern

    Electric Power Engineers LLC

    • Reduced large electrical networks to equivalent circuit models, tracing impedance paths and current flow across dozens of fault and operating scenarios.
    • Ran short-circuit (LG, LL, 3-phase), voltage ride-through and steady-state studies in PSSE across 20+ system cases, validating models and delivering technical reports.
    • PSSE
    • Fault analysis
    • Power flow
    • Technical reports

  5. Jan — Apr 2025

    Embedded Systems Intern

    SkyJack Inc. · Linamar Corp.

    • Analyzed CAN traces from boom-lift systems in PCAN Explorer to validate control thresholds and catch logic mismatches.
    • Generated CAN messages to simulate control inputs and assessed response speed and behaviour in MATLAB Simulink.
    • Automated firmware flashing for 5,000+ ZAPI inverters and built Python tools (PCAN / IXXAT) to verify COM IDs, cutting QA time by 70%.
    • CAN
    • Python
    • MATLAB / Simulink
    • PCAN

  6. Jul — Sep 2023

    Photonics Research Intern

    McMaster University · Faculty of Engineering

    • Designed photonic integrated circuit components, including an Archimedean spiral that reduced simulated bend loss and improved transmission bandwidth.
    • Evaluated waveguide geometries, mode profiles and propagation loss to optimize PIC layouts for fabrication.
    • Built MATLAB automation that halved laser-testing time, and authored an SOP for thermistor calibration.
    • PIC design
    • Waveguides
    • MATLAB
    • Lab automation
§ 04

Photography

The other end

Selected
Frames

Every frame starts as photons landing on a CMOS sensor, millions of tiny pixels converting light into charge and charge into bits. Outside of engineering, I spend my time behind the camera traveling and chasing good light.

Enter the gallery
§ 05

Contact

Hiring for your Hardware team, building something, or talking photography?

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